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sanyo electric co.,ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan ordering number : enn7813 62504tn (ot) no. 7813-1/16 overview the LV8224FN is a system motor driver ic that implements all the motor driver circuits needed for cd and md products. the LV8224FN provides a three-phase pwm spindle driver, a sled driver (either three-phase or pwm h bridge operation can be selected), and focus and tracking drivers (as two pwm h bridge driver channels). since the LV8224FN uses bicdmos devices, it can contribute to further miniaturization, thinner from factors, and lower power in end products. the adoption of the direct pwm sensorless drive method for the spindle driver makes it possible to implement high- efficiency motor drive with few external parts. functions ? pwm h bridge motor drivers (2 channels) ? three-phase stepping motor driver, and direct pwm sensorless motor driver sanyo semiconductors data sheet LV8224FN bi-cmos ic motor driver system in cd and md players any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein. specifications absolute maximum ratings at ta = 25c parameter symbol conditions ratings unit supply voltage v cc max 5.0 v output block supply voltage v s max 4.5 v predriver voltage (gate voltage) v g max 6.5 v output current i o max 0.8 a pd max1 independent ic 0.35 w allowable power dissipation pd max2 mounted on a 50.0 50.0 0.8 mm glass epoxy 1.10 w pcb (reference value) operating temperature topr C30 to +85 c storage temperature tstg C55 to +150 c recommended operating conditions at ta = 25c parameter symbol conditions ratings unit supply voltage v cc 1.9 to 4.0 v output block supply voltage v s 0 to v g C 3.0 v predriver voltage (gate voltage) v g v s + 3 to 6.3 v
no.7813- 2 /16 l v8224fn electrical characteristics at ta = 25 c, v cc = 2.3 v parameter symbol conditions ratings unit min typ max current drain 1 i cc 1 s/s pin: high 1.0 1.5 ma current drain 2 i cc 2 s/s pin: low (standby mode) 20 a [charge pump output] output voltage v g 5.4 5.9 6.2 v actuator block [position detector comparator block] input offset voltage v aofs C9 +9 mv common-mode input voltage range v acm 0 v cc v high-level output voltage v ach i o = C0.5 ma v cc C 0.5 v cc v low-level output voltage v acl i o = 0.5 ma 0.5 v [output block] (out1f/r, out2f/r, and suo to swo pins) source1 ron (h1) i o = 0.5 a, v s = 1.2 v, v g = 6 v, 0.4 0.6 forward transistor source2 ron (h2) i o = 0.5 a, v s = 1.2 v, v g = 6 v, 0.4 0.6 reverse transistor sink ron (l) i o = 0.5 a, v s = 1.2 v, v g = 6 v 0.4 0.6 source + sink ron (h+l) i o = 0.5 a, v s = 1.2 v, v g = 6 v 0.8 1.2 output transmission delay time t rise design target value* 0.1 1.0 s (h bridge) t fall design target value* 0.1 0.7 s minimum input pulse width tmin with the channel 1 and channel 2 pulse 200 ns (h bridge) widths 3 2/3 tmin, design target value * [decoder and actuator input pins] (in1f/r, in2f/r, and s1 to s3 pins) high-level input voltage range v ih v cc C 0.5 v cc v low-level input voltage range v il 0 0.5 v high-level actuator input pin current i inh when the input pin voltage is 2.3 v 9.5 13 a low-level actuator input pin current i inl when the input pin voltage is 0 v 1 a [mute pin] high-level input voltage range v muh mute off v cc C 0.5 v cc v low-level input voltage range v mul mute on 0 0.5 v high-level input pin current i muteh when the input pin voltage is 2.3 v 9.5 13 a low-level input pin current i mutel when the input pin voltage is 0 v 1 a continued on next page. * : design target value parameters are not tested.
no.7813- 3 /16 l v8224fn parameter symbol conditions ratings unit min typ max spindle motor driver block [output block] source1 ron (h1) i o = 0.5 a, v s = 1.2 v, v g = 6 v, 0.4 0.6 forward transistor source2 ron (h2) i o = 0.5 a, v s = 1.2 v, v g = 6 v, 0.4 0.6 reverse transistor sink ron (l) i o = 0.5 a, v s = 1.2 v, v g = 6 v 0.4 0.6 source + sink ron (h+l) i o = 0.5 a, v s = 1.2 v, v g = 6 v 0.8 1.2 [position detector comparator] input offset voltage v sofs C9 9 mv [startup oscillator pin] osc pin high-level voltage v osch 0.85 1.05 1.25 v osc pin low-level voltage v oscl 0.40 0.60 0.80 v [s/s pin] high-level input voltage range v ssh start v cc C 0.5 v cc v low-level input voltage range v ssl stop 0 0.5 v high-level input pin current i ssh when the input pin voltage is 2.3 v 9.5 13 a low-level input pin current i ssl when the input pin voltage is 0 v 1 a [break pin] high-level input voltage range v brh brake off v cc C 0.5 v cc v low-level input voltage range v brl brake on 0 0.5 v high-level input pin current i brkh when the input pin voltage is 2.3 v 9.5 13 a low-level input pin current i brkl when the input pin voltage is 0 v 1 a [pwm pin] high-level input voltage range v pwmh v cc C 0.5 v cc v low-level input voltage range v pwml 0 0.5 v high-level input pin current i pwmh when the input pin voltage is 2.3 v 9.5 13 a low-level input pin current i pwml when the input pin voltage is 0 v 1 a pwm input frequency v pwmin 190 khz [clk pin] high-level input voltage range v clkh v cc C 0.5 v cc v low-level input voltage range v clkl 0 0.5 v high-level input pin current i clkh when the input pin voltage is 2.3 v 9.5 13 a low-level input pin current i clkl when the input pin voltage is 0 v 1 a [fg output pin] high-level output voltage v fgh i o = C0.5 ma v cc C 0.5 v cc v low-level output voltage v fgl i o = 0.5 ma 0.5 v continued from preceding page. side view bottom view 0.4 7.2 top view 5.0 5.0 7.0 7.2 7.0 0.4 0.3 0.3 0.2 0.5 (0.75) 0.85max (0.8) 0.2 1 12 13 24 25 36 37 48 0 20 20 40 60 100 80 0.57 0.18 0.35 1.1 0 1.5 1.0 0.5 ambient temperature, t a c allo w able po wer dissipation, pdmax w il v00175 pd max t a independent ic mounted on a thermal resistance e v aluation pcb (50.0 50.0 0.8 mm glass epoxy pcb) package dimensions unit : mm 3272 sanyo : vqfn48 (7 7)
no.7813- 4 /16 l v8224fn mute in1, 2f in1, 2r out1, 2f out1, 2r h l l l l h h l h l h l h l h h h h l l l z z focus and tracking blocks mute s1 s2 s3 suo svo swo h l l l h l z h h l l h z l h l h l z h l h h h l l h z h l l h l z h h h l h z l h h l h h z z z h h h h z z z l z z z sled drive block stepping drive mode (when the 3/h pin (pin 47) is high) z: open mute s1 s2 suo svo h l l l l h h l h l h l h l h h h h l l l z z mute s3 swo h l l h h h l z sled drive block h bridge drive mode (when the 3/h pin (pin 47) is low) z: open notes: when the 3/h pin is set to select h bridge mode, suo and svo operate as pwm h bridge outputs according to the s1 and s2 inputs, and swo operates as a half-bridge circuit output according to the s3 input. actuator truth tables
no.7813- 5 /16 l v8224fn pin assignment vqfn48 (7 7) 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 swo slgnd slvs clk cp2 cp1 cpc1 cpc2 vg v cc 3/h suco uout spg nd spvs in1f in1r in2f in2r mute gnd pwm brk s/s LV8224FN svco swco spfg s1 s2 s3 slcom spcom spcin spfil soft osc svo suo out2r pgnd2 vs2 out2f out1r pgnd1 vs1 out1f wout vout top view
no.7813- 6 /16 l v8224fn pin functions pin no. pin name pin description equivalent circuit 48 1 2 suco svco swco sled driver block position detector comparator outputs v cc continued on next page. 3 spfg fg pulse output. this pin outputs a three hall sensor system equivalent pulse signal. 4 5 6 s1 s2 s3 three-phase sled block logic inputs. pins 35, 36, and 37 are the corresponding outputs. 10 k v cc 200 k 7 slcom sled driver block position detector comparator common input 1 k vg 7 11 soft spindle driver block drive current waveform selection. set this pin low when using a cored motor and high when using a coreless motor. 11 10 k v cc 12 osc startup oscillator connection. when this pin is connected to v cc , the startup frequency will be equivalent to f clk /4096, and connected to ground, that frequency will be f clk /3072. if any other startup frequency is to be set, insert a capacitor between this pin and ground. the startup frequency can be set freely by changing the value of the capacitor. 12 500 v cc 500
no.7813- 7 /16 l v8224fn pin no. pin name pin description equivalent circuit 8 spcom spindle motor common point connection 9 spcin position detector comparator differential input. insert a capacitor between this pin and the spfil pin (pin 10). 10 spfil waveform synthesis signal filter connection. insert a capacitor between this pin and the spcin pin (pin 9). continued on next page. 200 k vg 9 8 1 k 12 k vg 10 200 k 12 k 13 s/s spindle motor block start/stop control. a high-level input sets the block to start mode. 14 brk spindle motor block braking control. a low-level input sets the block to reverse torque braking. 15 pwm pwm signal input. the output transistor is on when this input is high. 17 mute muting control for the h bridge 1 and 2 blocks and the sled driver block. when a low level is input, these channel outputs all go to the high-impedance state. 21, 20 19, 18 in1f/r in2f/r actuator h bridge block logic inputs 40 clk logic circuit operation reference clock input. supply a frequency 32 times that of the spindle pwm frequency. 16 gnd small-signal system circuit ground 10 k v cc 200 k continued from preceding page.
no.7813- 8 /16 l v8224fn pin no. pin name pin description equivalent circuit 22 spvs spindle motor drive power supply. insert a capacitor between this pin and ground. 24 25 26 22 23 1 k 1 k 1 k 29 27 28 30 continued from preceding page. 24 25 26 uout vout wout spindle driver outputs. connect these pins to the spindle motor. 23 spgnd spindle output block ground 28 27, 30 29 vs1 out1f/r pgnd1 h bridge 1 output block. insert a capacitor between the vs1 pin (pin 28) and ground. 33 31 32 34 32 31, 34 33 vs2 out2f/r pgnd2 h bridge 2 output block. insert a capacitor between the vs2 pin (pin 32) and ground. 35 36 37 39 38 1 k 1 k 1 k 42 v cc 41 39 slvs sled motor drive power supply. insert a capacitor between this pin and ground. 35 36 37 suo svo swo sled driver outputs. connect these pins to the sled motor. 38 slgnd sled output block ground 42 cp1 charge pump step-up pulse output. insert a capacitor between this pin and the cpc1 pin (pin 43). leave this pin open when using this circuit as a 2 step-up circuit. 41 cp2 charge pump step-up pulse output. insert a capacitor between this pin and the cpc2 pin (pin 44). continued on next page.
no.7813- 9 /16 l v8224fn pin no. pin name pin description equivalent circuit 43 cpc1 charge pump step-up connection. insert a capacitor between this pin and the cp1 pin (pin 42). v cc 45 43 44 47 1 k v cc 1 k continued from preceding page. 44 cpc2 charge pump step-up connection. insert a capacitor between this pin and the cp2 pin (pin 41). 45 vg charge pump stepped up voltage output. insert a capacitor between this pin and ground. 46 v cc small-signal system power supply. insert a capacitor between this pin and ground. 47 3/h sled drive mode selection. a high-level input selects three-phase stepping mode, and a low-level input selects h bridge + half bridge mode. this pin must not be left open.
no.7813- 10 /16 l v8224fn block diagram slgnd 3/h spindle pre driver spgnd wout vout uout spvs waveform synthesizer spcom osc os c sel pwm spfg LV8224FN vs2 pre driver out2f pgnd1 vs1 logic in2f in2r pre driver out1f out1r logic in1f in1r mute out2r sled pre driver swo svo suo slvs waveform distributor waveform synthesizer slcom brk s3 s2 s1 logic vg v cc gnd clk pgnd2 cin fil swco svco suco cpc1 cp2 cpc2 charge pump cp1 1/n soft s/s sensorless logic sel
no.7813- 11 /16 l v8224fn sample application circuit 1 LV8224FN uout 32 33 34 35 36 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 5 4 3 2 1 6 7 8 9 10 11 12 37 38 39 40 41 42 43 44 45 46 47 48 spgnd spvs in1f in1r in2f in2r mute gnd pwm brk s/s osc soft spfil spcin spcom slcom s3 s2 s1 spfg swco svco suco to the sled motor to the spindle motor 3/h v cc vg cpc2 cpc1 cp1 cp2 clk slvs slgnd swo svo suo out2r pgnd2 vs2 out2f out1r pgnd1 vs1 out1f wout vout to slcom to spcom sled motor spindle motor vs dsp dsp dsp vs dsp vs vs notes startup with automatic oscillation mode sled three-phase stepping mode cored motor spindle motor mode capacitors must be inserted between each vs and pgnd pair, and between each v cc and gnd pair.
no.7813- 12 /16 l v8224fn application circuit example 2 LV8224FN uout 32 33 34 35 36 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 5 4 3 2 1 6 7 8 9 10 11 12 37 38 39 40 41 42 43 44 45 46 47 48 spgnd spvs in1f in1r in2f in2r mute gnd pwm brk s/s osc soft spfil spcin spcom slcom s3 s2 s1 spfg swco svco suco 3/h v cc vg cpc2 cpc1 cp1 cp2 clk slvs slgnd swo svo suo out2r pgnd2 vs2 out2f out1r pgnd1 vs1 out1f wout vout vs dsp vs sp vs vs vg v cc to the sled motor to the spindle motor slcom to sp sled motor spindle motor notes startup with internal oscillation control mode (l selected) sled three-phase stepping mode cored motor spindle motor mode using an external stepped-up power supply capacitors must be inserted between each vs and ground, between each v cc and ground, and between each vg and ground.
no.7813- 13 /16 l v8224fn LV8224FN functional description and notes on external components the LV8224FN is a system driver ic that implements, in a single chip, all the motor driver circuits required for cd and md players. since the LV8224FN provides a spindle motor driver (three-phase pwm sensorless drive), a sled stepping motor driver that supports either three-phase stepping or pwm h bridge drive, and two pwm h bridge drivers for the focus and tracking blocks, it can contribute to thinner form factors and further miniaturization in end products. since the spindle motor driver uses a direct pwm sensorless drive technique, it achieves high-efficiency motor drive with a minimal number of external components. read the following notes before designing driver circuits using the LV8224FN to design a system with fully satisfactory characteristics. output drive circuit and speed control methods the LV8224FN adopts the synchronous commutation direct pwm drive method to minimize power loss in the output circuits. low on-resistance dmos devices (total high and low side on-resistance: 0.8 , typical) are used as the output transistors. the spindle motor driver speed is controlled by brk and pwm signals provided by an external dsp. the pwm signal controls the sink side transistor. that transistor is switched according to the input duty of the signal input to the pwm pin (pin 15) to control the motor speed. (the sink side transistor is on when the pwm input is high, and off when the pwm input is low.) the LV8224FN also uses variable duty soft switching to achieve quieter motor drive. soft switching mode selection the LV8224FN spindle drive block uses variable pwm duty soft switching to reduce motor drive noise. the soft pin (pin 11) selects the soft switching drive mode, that is, it selects different conditions for optimally quiet drive depending on the motor structure (coil inductance). set the soft pin to the high level for coreless motors (motors with a low inductance) and to the low level for cored motors (motors with a high inductance) for optimal soft switching. although the soft pin has an mos input circuit, it does not have a built-in pull-up or pull-down resistor, and thus must be set to the high or low level. this pin must not be left open. s/s and mute circuits the s/s pin (pin 13) functions as the spindle motor drivers start/stop pin; a high-level input specifies that the operation is in the start state. the mute pin (pin 17) operates on all driver blocks other than the spindle block; a low-level input mutes these outputs. in the muted state, the corresponding drivers (h bridge and three-phase sled drivers) all go to the high-impedance state, regardless of the states of the logic inputs. since the s/s and mute pins operate independently, low-level inputs must be applied to both the s/s and mute pins to set the ic to the standby state (power saving mode). braking circuit the brk pin (pin 14) switches the direction of the torque applied by the spindle motor driver; when a low level is applied to the brk pin, the driver switches to reverse torque braking mode. when the motor decelerates to an adequately low speed in reverse torque braking mode, the driver switches to short-circuit braking mode to stop the motor. (note: the ic cannot be set to low-power mode at this time.) notes on the clk and pwm signals the LV8224FN clk pin (pin 40) is used as the sensorless logic reference clock, for step-up circuit pulse generation, and for other purposes. therefore, the clk signal must be supplied at all times when the LV8224FN is in start mode. the clk input signal must have a frequency 32 times that of the pwm input signal. we recommend that the clk input frequency be less than 6 mhz. fg output circuit the spfg pin (pin 3) is the spindle block fg output. it outputs a pulse signal equivalent to a three hall sensor fg output. this output has an mos circuit structure.
no.7813- 14 /16 l v8224fn spindle block position detector comparator circuit the spindle block position detection comparator circuit is provided to detect the position of the rotor using the back emf generated when the motor turns. the ic determines the timing with which the output block applies current to the motor based on the position information acquired by this circuit. startup problems due to comparator input noise can be resolved by inserting a capacitor (about 1000 to 4700 pf) between the spcin pin (pin 9) and the spfil pin (pin 10). note that if this capacitor is too large, the output commutation timing may be delayed at higher speeds and efficiency may be reduced. osc circuit the osc pin (pin 12) is an oscillator pin provided for sensorless motor startup commutation. the LV8224FN provides two main clock dividing modes and a self-oscillation mode. the main clock division modes are selected by setting the osc pin to either v cc or ground. the startup frequency is created by dividing the signal input to the clk pin (pin 40), and is either clk/4096 (when the osc pin is connected to v cc ) or clk/3072 (when the osc pin is connected to ground). self-oscillation mode is set up by inserting a capacitor between the osc pin and ground. when self-oscillation mode is selected, the osc pin starts self-oscillating, and that frequency becomes the startup frequency. the oscillator frequency can be adjusted by changing the value of the external capacitor (reducing the value of the capacitor increases the startup frequency). the number of external components can be reduced if there are no problems with the startup characteristics when the osc pin is connected to either v cc or ground. however, if there are problems, select self-oscillation mode and select a value of the capacitor that provides optimal startup characteristics. charge pump circuit the LV8224FN n-channel dmos output structure allows it to provide a charge pump based voltage step-up circuit. a voltage 3 times the v cc voltage (or about 6.0 v) can be acquired from the vg pin (pin 45) by inserting capacitors (recommended value: 0.1 f or larger) between the cp1 (pin 42) and cpc1 (pin 43) pins and between the cp2 (pin 41) and cpc2 (pin 44) pins. we recommend using this circuit with values such that the voltage relationship between the stepped-up voltage (vg) and the motor supply voltage (vs) is vg C vs 3 3.0 v. note that this circuit is designed so that the stepped-up voltage (vg) is clamped at about 6.0 vdc. a larger capacitor must be used on the vg pin if the ripple on the stepped-up voltage (vg) results in vgmax exceeding 6.5 v. observe the following points if the vg voltage is supplied from external circuits. ? the vg voltage supplied from the external circuits must not exceed the absolute maximum rating vgmax. ? the capacitors between the cp and cpc pins (pins 41 to 44) are not required. ? there is an ic-internal diode between the v cc and vg pins. therefore, supply voltages such that vcc > vg must never be applied to this ic. sled driver the LV8224FN sled driver block provides two output circuit structures: one appropriate for a three-phase motor and one appropriate for a dc motor. connect the 3/h pin (pin 47) to v cc to set the block to use the three-phase sensorless drive structure, and connect the 3/h pin to ground to set the block to use the pwh h bridge drive structure. the s1 to s3 pins (pins 4 to 6) are the sled driver block control inputs, and the signals are supplied by the dsp. the s1 to s3 pins have built-in pull-up resistors. the suc0 to swc0 pins (pins 48, 1, and 2) are the sled driver position detector comparator output pins. these signals are only output in three-phase stepping mode, and output the low-level potential in standby mode and pwm h bridge mode. these pins are used to feed back the sled motor speed and position information to the dsp or microcontroller. actuator block the LV8224FN incorporates two h bridge channels for use as actuator drivers for the focus and tracking systems. the logic input pin circuits incorporates pull-down resistors. a pwm signal is used for control, and the circuit supports synchronous commutation. the out1f/r output (pins 27 and 30) is the output corresponding to the in1f/r (pins 21 and 20) channel 1 control input, and the out2f/r output (pins 31 and 34) is the output corresponding to the in2f/r (pins 19 and 18) channel 2 control input. the figures show the dead band characteristics during motor control and the test circuit used for measuring those characteristics.
no.7813- 15 /16 l v8224fn notes on pcb pattern design the LV8224FN is a system driver ic implemented in a bi-dmos process; the ic chip includes bipolar circuits, mos logic circuits, and mos drive circuits integrated on the same chip. as a result, extreme care is required with respect to the pattern layout when designing application circuits. ? ground and v cc /v s wiring layout the LV8224FN ground and power supply pins are classified as follows. small-signal system ground pin ? gnd (pin 16) large-signal system ground pins ? pgnd1 (pin 29), pgnd2 (pin 33), spgnd (pin 23), slgnd (pin 38) small-signal system power supply pin ? v cc (pin 46) large-signal system power supply pins ? vs1 (pin 28), vs2 (pin 32), spvs (pin 22), slvs (pin 39) a capacitor must be inserted, as close as possible to the ic, between the small-signal system power supply pin (pin 46) and ground pin (pin 16). the large-signal system ground pins (pgnd1, pgnd2, spgnd, and slgnd) must be connected with the shortest possible lines, and furthermore in a manner such that there is no shared impedance with the small-signal system ground lines. capacitors must also be inserted, as close as possible to the ic, between the large-signal system power supply pins (vs1, vs2, spvs, and slvs) and the corresponding large-signal system ground pins. ? positioning the small-signal system external components the small-signal system external components that are also connected to ground must be connected to the small-signal system ground with lines that are as short as possible. ? notes on components connected between ic pins external components connected between ic pins must be connected using the shortest lines possible. the capacitor between cp1 (pin 42) and cpc1 (pin 43) the capacitor between cp2 (pin 41) and cpc2 (pin 44) the capacitor between spfil (pin 10) and spcin (pin 9) 100 80 60 40 20 20 40 60 80 100 10 8 6 4 2 0 2 4 6 8 10 actuator small-signal i/o characteristics in1f/r (%) (in1r is shown as negative.) the output is passed through 22 h inductors and smoothed with a low-pass filter consisting of a 2.0 resistor and two 1 f capacitors. in1f/r (%) (in1r is shown as negative.) the output is passed through 22 h inductors and smoothed with a low-pass filter consisting of a 2.0 resistor and two 1 f capacitors. out1 output voltage v (out1r is shown as negative.) out1 output voltage v (out1r is shown as negative.) v cc = 2.3 v, v s = 1.2 v, p wm = 132 khz (0 2.3 v) actuator small-signal i/o characteristics (magnified) v cc = 2.3 v, v s = 1.2 v, p wm = 132 khz (0 2.3v) 1.0 0.8 0.6 0.4 0.2 0.0 0.2 0.4 0.6 0.8 1.0 100 80 60 40 20 0 20 40 60 80 100 out1f out1r 2.0 22 h 1 f
ps no.7813- 16 /16 l v8224fn specifications of any and all sanyo products described or contained herein stipu late the performance , characteristics, and functions of the described products in the independent stat e, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's p roducts or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability product s. however, any and al l semiconductor products fail with some probability. it is possible that these pro babilistic failures coul d give rise to accidents or events that could endanger human lives, that could giv e rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt sa fety measures s o t hat these kinds of accidents or events cannot occur. such measures include but a re not limited to protectiv e circuits and error prevention circuits for safe design, redundant design, and st ructural design. in the event that any or all sanyo products(including technical data,services) d escribed o r contained herein are controlled under any of applicable local export control law s and regulations, such products m ust not be e xpor ted without obtaining the e xpor t license from the author ities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by a ny means, electronic o r mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co. , ltd. any and all information described or contained herein are subject to change with out notice due to product/technology improvement, etc. when designing equipment, refer to the "del ivery specification " for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for ex ample only ; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of inte llectual property rights or other rights of third parties. this catalog provides information as of june, 2004. specifications and information herein are subject to change without notice.

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